In input/output circuits, a bus holder has been used to maintain the previous voltage state (or logic state) on a logic signal bus until a new input signal is input, for example via a pad, when the bus/pad is floated. The bus holder often includes two inverters that are connected to each other. The voltage levels of an input/output signal may be diversified as diverse application products are released. Therefore, the input/output circuit also may be designed to enable diverse voltage levels to be processed. Accordingly, the input/output circuit may include the tolerant input/output buffer using a pass transistor and a bus holder, and can be used for application products that treat a wide range of input/output voltages.
FIG. 1 is a circuit diagram illustrating a conventional tolerant input/output buffer, and FIG. 2 is a circuit diagram illustrating another conventional tolerant input/output buffer.
Hereinafter, an operation of a bus holder used for the conventional tolerant input/output buffer and the tolerant input/output circuit will be explained with reference to FIGS. 1 and 2.
Referring to FIG. 1, the tolerant input/output buffer 100 includes a PAD that receives an external signal, an electrostatic discharge protection circuit 110, a pass transistor 120, a first inverter 130, a second inverter 140, a pass switch 150, and a buffer 160.
The PAD receives and outputs a signal from/to an external source. As used herein “PAD” means any input/output signal carrying line, whether or not in the shape of a pad. When an over-voltage caused by static electricity is applied toward a core logic (connected at Y) while a signal is received through the PAD, the electrostatic discharge protection circuit 110 supplies an additional passage for the over-voltage and protects the core logic by preventing the over-voltage from being transferred to the core logic. When the voltage level of the input signal received through the PAD is higher than an operation voltage range of the first inverter 130 or the buffer 160, the pass transistor 120 lowers the input voltage level and supplies the input signal having the lowered voltage level to the first inverter 130 and the buffer 160. A bus holder includes the first inverter 130, the second inverter 140, and the pass switch 150, in order to maintain the voltage of a node B1. The buffer 160 transfers the input signal received through the PAD and the pass transistor 120 to the core logic. A first power supply voltage of the electrostatic discharge protection circuit 110, the pass transistor 120, the first inverter 130, the second inverter 140, the buffer 160, and other circuits is, for example, 1.8 volts.
Hereinafter, when an input signal of 3.3 volts and the input signal of 1.8 volts are applied to the PAD, an operation of the tolerant input buffer 100 will be explained.
First, when the input signal of 3.3 volts is received through the PAD, the voltage at a connection node A1 between the PAD and the pass transistor 120 becomes 5 volts, and the voltage at a connection node B1 between the pass transistor 120 and the first inverter 130 becomes 1.0 volt.
Since the pass transistor 120 is an n-type MOS transistor, the node B1 outputs the voltage, which is lower than the power supply voltage (e.g., 1.8 volts) that is coupled to a gate of the pass transistor 120 by a threshold voltage Vth. In other words, when the voltage received through the PAD is higher than the power supply voltage of 1.8 volts, (1.8 volts—threshold voltage Vth) is output.
Therefore, even when the voltage of the input signal is much higher, the first inverter 130 and the buffer 160 are provided with the lowered input signal (i.e., 1.8 volts—threshold voltage Vth).
Consequentially, the voltage of the node B1 becomes 1.0 volt, and 1.0 volt is input to the buffer 160. Then, the lowered input signal is transferred to the core logic via the buffer 160. At this time, the first inverter 130, an input terminal of which is connected to the node B1, produces an output signal of 0 volts, and the second inverter 140 produces an output signal of 1.8 volts.
At the same time, the voltage of 1.0 volt is output to a node C1 via an n-type MOS transistor MN3 of the pass switch 150 that is connected to the node B1. However, since the node C1 is also connected with the output signal of the second inverter, the voltage of the node C1 is immediately increased to 1.8 volts.
Then, 1.8 volts of the voltage of the node C1 is transferred to node B1 by the PMOS transistor MP3 of the pass switch 150 so that the voltage of node B1 is raised to 1.8 volts. In this state, when the input signal of the PAD is removed, the PAD may become a floating state, and thus a signal having a voltage level of the floating state may be applied to the core logic.
However, when the bus holder is provided as described in FIG. 1, the node C1 is maintained at 1.8 volts and the node B1 is maintained at 1.8 volts by the pass switch 150. Thereby, the input state of the buffer 160 is maintained at a previous state of 1.8 volts.
When the input signal is 1.8 volts, only the voltage of the node A1 is different compared with the case in which the input signal is 3.3 volts. After passing through the pass transistor 120, the node B1 becomes 1.0 volt. Accordingly, the same operation as the case in which the input signal is 3.3 volts is performed.
The above-described tolerant input/output buffer 100 can operate regardless of the input voltage range and enables the bus holder to stably maintain a previous logic state when the PAD is floated. However since an initial voltage (e.g., 1.0 volt) of the node B1 is lower than the power supply voltage of 1.8 volts, and is close to the threshold voltage, namely the power supply voltage/2 (i.e., 0.9 volt) of the buffer 160, characteristics of a tolerant input cell may be deteriorated.
Particularly, it may be difficult to obtain a design margin for a Schmidt trigger's input cell when the buffer 160 is a Schmidt trigger. Since the Schmidt trigger has a hysteresis characteristic, the Schmidt trigger can stably operate when the input voltage is much higher than the threshold voltage (e.g., the power supply voltage/2) of the Schmidt trigger. In the tolerant input/output buffer of FIG. 1, the difference between the input voltage (i.e., 1.0 volt) of the Schmidt trigger, i.e., the buffer 160 and the threshold voltage (i.e., 0.9 volt) of the Schmidt trigger may be small (i.e., 0.1 volt). Accordingly, the Schmidt trigger may not operate normally.
Therefore, a circuit that enables the input voltage level of the buffer 160 to be higher than the threshold voltage (the power supply voltage/2) of the Schmidt trigger may be desired. An alternative conventional device is shown in FIG. 2.
FIG. 2 is a circuit diagram illustrating a conventional tolerant input/output buffer different from FIG. 1.
The tolerant input/output buffer may include a PAD, a static protection circuit 210, a first inverter 230, a second inverter 240, a pass switch 250, and a buffer 260. The tolerant input/output buffer of FIG. 2 is different from the tolerant input/output buffer of FIG. 1 in that the pass transistor 120, which lowers the voltage level of the input signal, is not used and the pass switch 250 includes only an n-type MOS transistor.
Since the pass transistor is not used so as to maintain the input voltage level of the buffer 260 at a high level, the input signal that passes through the PAD is not lowered and is transferred to a node A2.
Accordingly, since the input voltage of the buffer 260 can become higher than the threshold voltage of the Schmidt trigger, the possibility for an abnormal operation of the buffer 260 may be reduced.
When the input signal is 1.8 volts, and the pass switch 250 includes an n-type MOS transistor MN3 and a p-type MOS transistor MP3, the node A2 initially maintains 1.8 volts, and a node C2 is also maintained at 1.8 volts by the first inverter 230 and the second inverter 240.
When the PAD is floated, a node C2 can be maintained at 1.8 volts by an output the second inverter 240, and the node A2 can be maintained at 1.8 volts through the p-type MOS transistor of the pass switch 250.
However, when the input signal is 3.3 volts, the node A2 initially applies 3.3 volts. The voltage of the node A2 enables the node C2 to be maintained at 3.3 volts by the p-type MOS transistor MP3 of the pass switch 250. This may create a problem that the p-type MOS transistor of the second inverter is turned on, and thus inverse current may flow.
In order to solve the potential problem, the pass switch 250 includes only the n-type MOS transistor MN3 without using the p-type MOS transistor MP3. However, when the pass switch 250 is constituted only of the n-type MOS transistor without using the pass transistor as shown in FIG. 2, there also may be a problem in that the voltage of the node A2 is lowered after a predetermined time from the start of the floating of the PAD.
It is desirable for the level of the input voltage to be maintained. However, since the pass switch 250 is constituted only of the n-type MOS transistor MN3 and the node C2 outputs the voltage of 1.0 volt (i.e., the power supply voltage of 1.8 volts—the threshold voltage of the n-type MOS transistor MN3), the voltage of the node C2 may be lowered and may not maintain the input voltage level.